Technical Field
The present disclosure relates to semiconductor device fabrication, and more specifically, to methods of forming a semiconductor fin, or a finFET including the semiconductor fin, with a carbon dopant therein for limiting dopant diffusion in the fin.
Related Art
Fin-type field effect transistors (finFET) are used widely in advanced complementary metal-oxide semiconductor (CMOS) technologies. During finFET fabrication, a semiconductor fin is formed and a gate is formed perpendicular across the semiconductor fin. An epitaxial layer including n-type or p-type dopant is formed on the fin adjacent the gate, and an anneal is performed to diffuse the dopants from the epitaxial layer into a source/drain regions of the fin adjacent the gate and, to a lesser degree, a channel region of the fin under the gate. The dopants create the source/drain regions and a channel under the gate in the semiconductor fin that allow the finFET to operate.
One challenge in fabricating a finFET and other three-dimensional CMOS devices is controlling the concentration of dopant diffused from the dopant providing epitaxial layer, e.g., into the channel region and the source and drain regions of a finFET. One approach to controlling the dopant diffusion is introducing a carbon dopant by ion implantation, e.g., into the fin adjacent the channel region. Carbon has proven to be very effective to limit boron (B)(p-type) and phosphorus (P)(n-type) dopant diffusion in silicon. However, introducing a conformal carbon dopant is becoming more difficult in a number of ways. With respect to finFETs and other three-dimensional structures, carbon doping by conventional ion implantation is challenging because non-planer structures block the implant beam, especially at smaller technology nodes such as those with wire dimensions below 10 nanometers. As a result, carbon ion implant doping is not uniform across a semiconductor fin, comparing for example a top of the fin to a side of the fin. This non-uniform carbon doping causes non-uniform dopant out-diffusion from the conformal epitaxial layer between the top of the fin versus sides of the fin in three-dimensional structures, which creates a number of issues for smaller device features. One issue includes drain-induced barrier loading (DIBL), which refers to the reduction of threshold voltage at which the FET turns on caused by the shorter distances between source and drain regions, i.e., short channel effects. Another issue for bulk substrates includes ensuring device isolation between adjacent finFETs.